/* Date Stamp: 8/23/2014 */

#ifndef IIO_DFX_VTD_h
#define IIO_DFX_VTD_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_DFX_VTD_DEV 7                                                          */
/* IIO_DFX_VTD_FUN 4                                                          */

/* VID_IIO_DFX_VTD_REG supported on:                                          */
/*       IVT_EP (0x2003C000)                                                  */
/*       IVT_EX (0x2003C000)                                                  */
/*       HSX (0x2003C000)                                                     */
/*       BDX (0x2003C000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_DFX_VTD_REG 0x12022000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_DFX_VTD_REG supported on:                                          */
/*       IVT_EP (0x2003C002)                                                  */
/*       IVT_EX (0x2003C002)                                                  */
/*       HSX (0x2003C002)                                                     */
/*       BDX (0x2003C002)                                                     */
/* Register default value on IVT_EP:    0x0E1C                                */
/* Register default value on IVT_EX:    0x0E1C                                */
/* Register default value on HSX:       0x2F1C                                */
/* Register default value on BDX:       0x6F1C                                */
#define DID_IIO_DFX_VTD_REG 0x12022002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100011100 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel QPI
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C004)                                                  */
/*       IVT_EX (0x2003C004)                                                  */
/*       HSX (0x2003C004)                                                     */
/*       BDX (0x2003C004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_DFX_VTD_REG 0x12022004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RO, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RO, default = 1'b0 
       1
     */
    UINT16 sce : 1;
    /* sce - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 mwie : 1;
    /* mwie - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 perre : 1;
    /* perre - Bits[6:6], RW, default = 1'b0 
       1
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RW, default = 1'b0 
       1
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RO, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C006)                                                  */
/*       IVT_EX (0x2003C006)                                                  */
/*       HSX (0x2003C006)                                                     */
/*       BDX (0x2003C006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_DFX_VTD_REG 0x12022006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxstat : 1;
    /* intxstat - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fb2b : 1;
    /* fb2b - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 mdpe : 1;
    /* mdpe - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 devselt : 2;
    /* devselt - Bits[10:9], RO, default = 2'b00 
       1
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RO, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RO, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_DFX_VTD_REG supported on:                                          */
/*       IVT_EP (0x1003C008)                                                  */
/*       IVT_EX (0x1003C008)                                                  */
/*       HSX (0x1003C008)                                                     */
/*       BDX (0x1003C008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_DFX_VTD_REG 0x12021008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x1003C009)                                                  */
/*       IVT_EX (0x1003C009)                                                  */
/*       HSX (0x1003C009)                                                     */
/*       BDX (0x1003C009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_DFX_VTD_REG 0x12021009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.7.4.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_DFX_VTD_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C00A)                                                  */
/*       IVT_EX (0x2003C00A)                                                  */
/*       HSX (0x2003C00A)                                                     */
/*       BDX (0x2003C00A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_DFX_VTD_REG 0x1202200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x1003C00C)                                                  */
/*       IVT_EX (0x1003C00C)                                                  */
/*       HSX (0x1003C00C)                                                     */
/*       BDX (0x1003C00C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_DFX_VTD_REG 0x1202100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CLSR_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* PLAT_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x1003C00D)                                                  */
/*       IVT_EX (0x1003C00D)                                                  */
/*       HSX (0x1003C00D)                                                     */
/*       BDX (0x1003C00D)                                                     */
/* Register default value:              0x00                                  */
#define PLAT_IIO_DFX_VTD_REG 0x1202100D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x00d
 */
typedef union {
  struct {
    UINT8 primary_latency_timer : 8;
    /* primary_latency_timer - Bits[7:0], RO, default = 8'b00000000 
       Not applicable to PCI-Express. Hardwired to 00h.
     */
  } Bits;
  UINT8 Data;
} PLAT_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_DFX_VTD_REG supported on:                                          */
/*       IVT_EP (0x1003C00E)                                                  */
/*       IVT_EX (0x1003C00E)                                                  */
/*       HSX (0x1003C00E)                                                     */
/*       BDX (0x1003C00E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_DFX_VTD_REG 0x1202100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* BIST_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x1003C00F)                                                  */
/*       IVT_EX (0x1003C00F)                                                  */
/*       HSX (0x1003C00F)                                                     */
/*       BDX (0x1003C00F)                                                     */
/* Register default value:              0x00                                  */
#define BIST_IIO_DFX_VTD_REG 0x1202100F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x00f
 */
typedef union {
  struct {
    UINT8 bist_tests : 8;
    /* bist_tests - Bits[7:0], RO, default = 8'b00000000 
       Not supported. Hardwired to 00h
     */
  } Bits;
  UINT8 Data;
} BIST_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x2003C02C)                                                  */
/*       IVT_EX (0x2003C02C)                                                  */
/*       HSX (0x2003C02C)                                                     */
/*       BDX (0x2003C02C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIO_DFX_VTD_REG 0x1202202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b1000000010000110 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* SDID_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x2003C02E)                                                  */
/*       IVT_EX (0x2003C02E)                                                  */
/*       HSX (0x2003C02E)                                                     */
/*       BDX (0x2003C02E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_DFX_VTD_REG 0x1202202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x1003C034)                                                  */
/*       IVT_EX (0x1003C034)                                                  */
/*       HSX (0x1003C034)                                                     */
/*       BDX (0x1003C034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_DFX_VTD_REG 0x12021034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* INTL_IIO_DFX_VTD_REG supported on:                                         */
/*       IVT_EP (0x1003C03C)                                                  */
/*       IVT_EX (0x1003C03C)                                                  */
/*       HSX (0x1003C03C)                                                     */
/*       BDX (0x1003C03C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_DFX_VTD_REG 0x1202103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x1003C03D)                                                  */
/*       IVT_EX (0x1003C03D)                                                  */
/*       HSX (0x1003C03D)                                                     */
/*       BDX (0x1003C03D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_DFX_VTD_REG 0x1202103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* MINGNT_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x1003C03E)                                                  */
/*       IVT_EX (0x1003C03E)                                                  */
/*       HSX (0x1003C03E)                                                     */
/*       BDX (0x1003C03E)                                                     */
/* Register default value:              0x00                                  */
#define MINGNT_IIO_DFX_VTD_REG 0x1202103E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x03e
 */
typedef union {
  struct {
    UINT8 mgv : 8;
    /* mgv - Bits[7:0], RO, default = 8'b00000000 
       The Device does not burst as a PCI compliant master.
     */
  } Bits;
  UINT8 Data;
} MINGNT_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* MAXLAT_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x1003C03F)                                                  */
/*       IVT_EX (0x1003C03F)                                                  */
/*       HSX (0x1003C03F)                                                     */
/*       BDX (0x1003C03F)                                                     */
/* Register default value:              0x00                                  */
#define MAXLAT_IIO_DFX_VTD_REG 0x1202103F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x03f
 */
typedef union {
  struct {
    UINT8 mlv : 8;
    /* mlv - Bits[7:0], RO, default = 8'b00000000 
       The Device has no specific requirements for how often it needs to access the PCI 
       bus. 
     */
  } Bits;
  UINT8 Data;
} MAXLAT_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C040)                                                  */
/*       IVT_EX (0x4003C040)                                                  */
/*       HSX (0x4003C040)                                                     */
/*       BDX (0x4003C040)                                                     */
/* Register default value:              0x00920010                            */
#define PXPCAP_IIO_DFX_VTD_REG 0x12024040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x040
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b00000000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0010 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0 
       N/A for integrated endpoints
     */
    UINT32 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[29:25], RO, default = 5'b00000 
       N/A for this device
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DEVCAP_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C044)                                                  */
/*       IVT_EX (0x4003C044)                                                  */
/*       HSX (0x4003C044)                                                     */
/*       BDX (0x4003C044)                                                     */
/* Register default value:              0x00008000                            */
#define DEVCAP_IIO_DFX_VTD_REG 0x12024044
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x044
 */
typedef union {
  struct {
    UINT32 max_payload_size_supported : 3;
    /* max_payload_size_supported - Bits[2:0], RO, default = 3'b000  */
    UINT32 phantom_functions_supported : 2;
    /* phantom_functions_supported - Bits[4:3], RO, default = 2'b00  */
    UINT32 extended_tag_field_supported : 1;
    /* extended_tag_field_supported - Bits[5:5], RO, default = 1'b0  */
    UINT32 endpoint_l0s_acceptable_latency : 3;
    /* endpoint_l0s_acceptable_latency - Bits[8:6], RO, default = 3'b000  */
    UINT32 endpoint_l1_acceptable_latency : 3;
    /* endpoint_l1_acceptable_latency - Bits[11:9], RO, default = 3'b000  */
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[12:12], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[13:13], RO, default = 1'b0  */
    UINT32 power_indicator_present_on_device : 1;
    /* power_indicator_present_on_device - Bits[14:14], RO, default = 1'b0  */
    UINT32 role_based_error_reporting : 1;
    /* role_based_error_reporting - Bits[15:15], RO, default = 1'b1  */
    UINT32 rsvd_16 : 2;
    /* rsvd_16 - Bits[17:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 captured_slot_power_limit_value : 8;
    /* captured_slot_power_limit_value - Bits[25:18], RO, default = 8'b00000000  */
    UINT32 captured_slot_power_limit_scale : 2;
    /* captured_slot_power_limit_scale - Bits[27:26], RO, default = 2'b00  */
    UINT32 rsvd_28 : 4;
    /* rsvd_28 - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DEVCON_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C048)                                                  */
/*       IVT_EX (0x2003C048)                                                  */
/*       HSX (0x2003C048)                                                     */
/*       BDX (0x2003C048)                                                     */
/* Register default value:              0x0000                                */
#define DEVCON_IIO_DFX_VTD_REG 0x12022048
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * The PCI Express Device Control register controls PCI Express specific 
 * capabilities parameters associated with the device. 
 */
typedef union {
  struct {
    UINT16 correctable_error_reporting_enable : 1;
    /* correctable_error_reporting_enable - Bits[0:0], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 non_fatal_error_reporting_enable : 1;
    /* non_fatal_error_reporting_enable - Bits[1:1], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 fatal_error_reporting_enable : 1;
    /* fatal_error_reporting_enable - Bits[2:2], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 unsupported_request_reporting_enable : 1;
    /* unsupported_request_reporting_enable - Bits[3:3], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 enable_relaxed_ordering : 1;
    /* enable_relaxed_ordering - Bits[4:4], RO, default = 1'b0 
       For most parts, writes from CB DMA are relaxed ordered, except for DMA 
       completion writes. But the fact that CB DMA writes are relaxed ordered is not 
       very useful except when the writes are also non-snooped. If the writes are 
       snooped, relaxed ordering does not provide any particular advantage based on IIO 
       uArch. But when writes are non-snooped, relaxed ordering is required to get good 
       BW and this bit is expected to be set. If this bit is clear, NS writes will get 
       very poor performance. 
     */
    UINT16 max_payload_size : 3;
    /* max_payload_size - Bits[7:5], RO, default = 3'b000 
       N/A for CB DMA
     */
    UINT16 extended_tag_field_enable : 1;
    /* extended_tag_field_enable - Bits[8:8], RO, default = 1'b0  */
    UINT16 phantom_functions_enable : 1;
    /* phantom_functions_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to CB DMA since it never uses phantom functions as a requester.
     */
    UINT16 auxiliary_power_management_enable : 1;
    /* auxiliary_power_management_enable - Bits[10:10], RO, default = 1'b0 
       Not applicable to CB DMA
     */
    UINT16 enable_no_snoop : 1;
    /* enable_no_snoop - Bits[11:11], RO, default = 1'b0 
       For CB DMA, when this bit is clear, all DMA transactions must be snooped. When 
       set, DMA transactions to main memory can utilize No Snoop optimization under the 
       guidance of the device driver. 
     */
    UINT16 max_read_request_size : 3;
    /* max_read_request_size - Bits[14:12], RO, default = 3'b000 
       N/A to CB DMA since it does not issue tx on PCIE
     */
    UINT16 rsvd : 1;
    /* rsvd - Bits[15:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVCON_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DEVSTS_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C04A)                                                  */
/*       IVT_EX (0x2003C04A)                                                  */
/*       HSX (0x2003C04A)                                                     */
/*       BDX (0x2003C04A)                                                     */
/* Register default value:              0x0000                                */
#define DEVSTS_IIO_DFX_VTD_REG 0x1202204A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x04a
 */
typedef union {
  struct {
    UINT16 correctable_error_detected : 1;
    /* correctable_error_detected - Bits[0:0], RO, default = 1'b0  */
    UINT16 non_fatal_error_detected : 1;
    /* non_fatal_error_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 fatal_error_detected : 1;
    /* fatal_error_detected - Bits[2:2], RO, default = 1'b0  */
    UINT16 unsupported_request_detected : 1;
    /* unsupported_request_detected - Bits[3:3], RO, default = 1'b0  */
    UINT16 aux_power_detected : 1;
    /* aux_power_detected - Bits[4:4], RO, default = 1'b0  */
    UINT16 transactions_pending : 1;
    /* transactions_pending - Bits[5:5], RO, default = 1'b0  */
    UINT16 rsvd : 10;
    /* rsvd - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVSTS_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* LNKCAP_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C04C)                                                  */
/*       IVT_EX (0x4003C04C)                                                  */
/*       HSX (0x4003C04C)                                                     */
/*       BDX (0x4003C04C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP_IIO_DFX_VTD_REG 0x1202404C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x04c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* LNKSTS_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x2003C052)                                                  */
/*       IVT_EX (0x2003C052)                                                  */
/*       HSX (0x2003C052)                                                     */
/*       BDX (0x2003C052)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS_IIO_DFX_VTD_REG 0x12022052
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x052
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* LNKCAP2_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C06C)                                                  */
/*       IVT_EX (0x4003C06C)                                                  */
/*       HSX (0x4003C06C)                                                     */
/*       BDX (0x4003C06C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP2_IIO_DFX_VTD_REG 0x1202406C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x06c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP2_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* LNKCON2_OLD_IIO_DFX_VTD_REG supported on:                                  */
/*       IVT_EP (0x2003C070)                                                  */
/*       IVT_EX (0x2003C070)                                                  */
/*       HSX (0x2003C070)                                                     */
/*       BDX (0x2003C070)                                                     */
/* Register default value:              0x0000                                */
#define LNKCON2_OLD_IIO_DFX_VTD_REG 0x12022070
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x070
 */
typedef union {
  struct {
    UINT16 active_state_link_pm_control : 2;
    /* active_state_link_pm_control - Bits[1:0], RO, default = 2'b00  */
    UINT16 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 read_completion_boundary : 1;
    /* read_completion_boundary - Bits[3:3], RO, default = 1'b0  */
    UINT16 link_disable : 1;
    /* link_disable - Bits[4:4], RO, default = 1'b0  */
    UINT16 retrain_link : 1;
    /* retrain_link - Bits[5:5], RO, default = 1'b0  */
    UINT16 common_clock_configuration : 1;
    /* common_clock_configuration - Bits[6:6], RO, default = 1'b0  */
    UINT16 extended_synch : 1;
    /* extended_synch - Bits[7:7], RO, default = 1'b0  */
    UINT16 enable_clock_power_management_na : 1;
    /* enable_clock_power_management_na - Bits[8:8], RO, default = 1'b0  */
    UINT16 hardware_autonomous_width_disable_ioh : 1;
    /* hardware_autonomous_width_disable_ioh - Bits[9:9], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_interrupt_enable : 1;
    /* link_bandwidth_management_interrupt_enable - Bits[10:10], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_interrupt_enable : 1;
    /* link_autonomous_bandwidth_interrupt_enable - Bits[11:11], RO, default = 1'b0  */
    UINT16 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} LNKCON2_OLD_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* LNKSTS2_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x2003C072)                                                  */
/*       IVT_EX (0x2003C072)                                                  */
/*       HSX (0x2003C072)                                                     */
/*       BDX (0x2003C072)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS2_IIO_DFX_VTD_REG 0x12022072
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x072
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS2_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* SLTCAP2_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C074)                                                  */
/*       IVT_EX (0x4003C074)                                                  */
/*       HSX (0x4003C074)                                                     */
/*       BDX (0x4003C074)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP2_IIO_DFX_VTD_REG 0x12024074
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x074
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RO, default = 1'b0  */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RO, default = 1'b0  */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RO, default = 1'b0  */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RO, default = 1'b0  */
    UINT32 hotplug_surprise : 1;
    /* hotplug_surprise - Bits[5:5], RO, default = 1'b0  */
    UINT32 hotplug_capable : 1;
    /* hotplug_capable - Bits[6:6], RO, default = 1'b0  */
    UINT32 slot_power_limit_value : 8;
    /* slot_power_limit_value - Bits[14:7], RO, default = 8'b00000000  */
    UINT32 slot_power_limit_scale : 2;
    /* slot_power_limit_scale - Bits[16:15], RO, default = 2'b00  */
    UINT32 electromechanical_interlock_present : 1;
    /* electromechanical_interlock_present - Bits[17:17], RO, default = 1'b0  */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0  */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RO, default = 13'b0000000000000  */
  } Bits;
  UINT32 Data;
} SLTCAP2_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* SLTSTS2_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x2003C07A)                                                  */
/*       IVT_EX (0x2003C07A)                                                  */
/*       HSX (0x2003C07A)                                                     */
/*       BDX (0x2003C07A)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS2_IIO_DFX_VTD_REG 0x1202207A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x07a
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RO, default = 1'b0  */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RO, default = 1'b0  */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RO, default = 1'b0  */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RO, default = 1'b0  */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO, default = 1'b0  */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO, default = 1'b0  */
    UINT16 electromechanical_latch_status : 1;
    /* electromechanical_latch_status - Bits[7:7], RO, default = 1'b0  */
    UINT16 data_link_layer_state_changed : 1;
    /* data_link_layer_state_changed - Bits[8:8], RO, default = 1'b0  */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS2_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTD_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG supported on:                        */
/*       HSX (0x4003C108)                                                     */
/*       BDX (0x4003C108)                                                     */
/* Register default value:              0x00000000                            */
#define VTD_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG 0x12024108

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iivt4 debug signal sets drives the debug ring 
 * output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_0 : 4;
    /* dbg_ev_swiz_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_1 : 4;
    /* dbg_ev_swiz_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_2 : 4;
    /* dbg_ev_swiz_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_3 : 4;
    /* dbg_ev_swiz_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_4 : 4;
    /* dbg_ev_swiz_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_5 : 4;
    /* dbg_ev_swiz_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_6 : 4;
    /* dbg_ev_swiz_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_7 : 4;
    /* dbg_ev_swiz_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} VTD_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* VTD_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG supported on:                        */
/*       HSX (0x4003C10C)                                                     */
/*       BDX (0x4003C10C)                                                     */
/* Register default value:              0x00000000                            */
#define VTD_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG 0x1202410C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iivt4 debug signal sets drives the debug ring 
 * output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_8 : 4;
    /* dbg_ev_swiz_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[29:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xor_mode : 1;
    /* xor_mode - Bits[30:30], RWS_L, default = 1'b0 
       Puts the debug muxes into XOR mode instead of MUX mode for scanout coverage.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_mux_en : 1;
    /* dbg_mux_en - Bits[31:31], RWS_L, default = 1'b0 
       Turns on the debug muxes (clocks, etc).
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} VTD_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* VTD_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG supported on:                         */
/*       HSX (0x4003C110)                                                     */
/*       BDX (0x4003C110)                                                     */
/* Register default value:              0x00000000                            */
#define VTD_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG 0x12024110

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iivt4 debug signal sets will be muxed onto 
 * the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 4;
    /* dbg_ev_set_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 4;
    /* dbg_ev_set_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 4;
    /* dbg_ev_set_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 4;
    /* dbg_ev_set_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_4 : 4;
    /* dbg_ev_set_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_5 : 4;
    /* dbg_ev_set_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_6 : 4;
    /* dbg_ev_set_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_7 : 4;
    /* dbg_ev_set_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} VTD_DBG_MUX_INT_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* VTD_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG supported on:                         */
/*       HSX (0x4003C114)                                                     */
/*       BDX (0x4003C114)                                                     */
/* Register default value:              0x00000000                            */
#define VTD_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG 0x12024114

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iivt4 debug signal sets will be muxed onto 
 * the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_8 : 4;
    /* dbg_ev_set_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 28;
    /* rsvd - Bits[31:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTD_DBG_MUX_INT_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* VTDDEBUGREG0_IIO_DFX_VTD_REG supported on:                                 */
/*       IVT_EP (0x4003C118)                                                  */
/*       IVT_EX (0x4003C118)                                                  */
/*       HSX (0x4003C118)                                                     */
/*       BDX (0x4003C118)                                                     */
/* Register default value on IVT_EP:    0x00000000                            */
/* Register default value on IVT_EX:    0x00000000                            */
/* Register default value on HSX:       0x00000800                            */
/* Register default value on BDX:       0x00000800                            */
#define VTDDEBUGREG0_IIO_DFX_VTD_REG 0x12024118


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.7.4.CFG.xml.
 * This register contains defeature bits for the VT-d block.
 */
typedef union {
  struct {
    UINT32 rsvd : 1;
    /* rsvd - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 vteccdis : 1;
    /* vteccdis - Bits[1:1], RWS_L, default = 1'b0 
       VT Disable Parity CheckDisables parity check for read completions
       0: Enable parity check
       1: Disable parity check
     */
    UINT32 vtinvd : 4;
    /* vtinvd - Bits[5:2], RWS_L, default = 4'b0000 
       VT Invalidation Degradation controls[5]: Degrades TLB Domain down to global.
       [4]: Degrades TLB PGI down to global.
       [3]: Degrades TLB PGI down to domain.
       [2]: Degrades context cache domain to global.
     */
    UINT32 vtud_debug : 21;
    /* vtud_debug - Bits[26:6], RWS_L, default = 21'b000000000000000100000 
       The following bits in this field are used as follows.
       
       [12]: vt_dis_isoch_pref_fix
       [11]: vt_en_tcam_cmp_wr
       [10]: vt_en_inv_all_pending
       [9]: vt_en_inv_all
       [8]: vt_drain_vc1
       [7]: vt_dis_vld_cmt_replacement (when vt_dis_ats_cc_cmp=0)
       [6]: PSMIEn (Enables PSMI_Wipe to VT-d)
       
       If vtgenctrl2.tlb_hold_fetch_insert=1 then vtddebugreg0.vt_en_tcam_cmp_wr must 
       be set to 1. 
     */
    UINT32 tlb_passthru_sp_size : 1;
    /* tlb_passthru_sp_size - Bits[27:27], RWS_L, default = 1'b0 
       untranslated passthru super page size:
       0 - 1G superpage size, 1 - infinite superpage size
     */
    UINT32 tlb_dis_ut_passthru_superpage : 1;
    /* tlb_dis_ut_passthru_superpage - Bits[28:28], RWS_L, default = 1'b0 
       Set this to 1 to disable allocating superpages for at=0, tt=01 traffic.
       If you set vtgenctrl2.tlb_allow_b2b_victims=0, you also need to set 
       vtddebugreg0.tlb_dis_ut_passthru_superpage=1. 
     */
    UINT32 tlb_dis_hsd254725_fix : 1;
    /* tlb_dis_hsd254725_fix - Bits[29:29], RWS_L, default = 1'b0 
       Set this to 1 to disable the fix for HSX HSD 254725. Remove this in future 
       products. 
     */
    UINT32 vtdiscarpt : 1;
    /* vtdiscarpt - Bits[30:30], RWS_L, default = 1'b0 
       Disable CA Reporting0: Enable Completer Abort Reporting.
       1: Disable Completer Abort Reporting.
     */
    UINT32 vtinhmsi : 1;
    /* vtinhmsi - Bits[31:31], RWS_L, default = 1'b0 
       Inhibit MSI.0: Allow MSI generation.
       1: Inhibit MSI generation.
     */
  } Bits;
  UINT32 Data;
} VTDDEBUGREG0_IIO_DFX_VTD_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* VTDDEBUGREG1_IIO_DFX_VTD_REG supported on:                                 */
/*       IVT_EP (0x4003C11C)                                                  */
/*       IVT_EX (0x4003C11C)                                                  */
/*       HSX (0x4003C11C)                                                     */
/*       BDX (0x4003C11C)                                                     */
/* Register default value:              0x00000000                            */
#define VTDDEBUGREG1_IIO_DFX_VTD_REG 0x1202411C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register controls the cache masking and enable bits for the VT-d block in 
 * each XP cluster. 
 */
typedef union {
  struct {
    UINT32 cachemask : 7;
    /* cachemask - Bits[6:0], RWS_L, default = 7'b0000000 
       1
     */
    UINT32 maskenable : 4;
    /* maskenable - Bits[10:7], RWS_L, default = 4'b0000 
       1
     */
    UINT32 debug_reg1 : 21;
    /* debug_reg1 - Bits[31:11], RWS_L, default = 21'b000000000000000000000 
       1
     */
  } Bits;
  UINT32 Data;
} VTDDEBUGREG1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPAREINJCTL_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C120)                                                  */
/*       IVT_EX (0x4003C120)                                                  */
/*       HSX (0x4003C120)                                                     */
/*       BDX (0x4003C120)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPAREINJCTL_IIO_DFX_VTD_REG 0x12024120
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains the error injection mask register to determine which bits 
 * get corrupted for error detection testing.  
 */
typedef union {
  struct {
    UINT32 pf : 4;
    /* pf - Bits[3:0], RWS, default = 4'b0000 
       Protection Flip bitsThis mask is used to invert the corresponding parity bit 
       assigned to the byte, word, or dword of the data. Refer to Table 14-68 for 
       details. 
       Note: If there is only 1 parity bit for a RAM then a PF bit is not necessary. By 
       selecting the BPS and an error enable will invert the parity bit (assuming the 
       selected EINJ has triggered) 
     */
    UINT32 rsvd_4 : 20;
    /* rsvd_4 - Bits[23:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 bps : 4;
    /* bps - Bits[27:24], RWS, default = 4'b0000 
       Buffer-Path select:
       0000: IOTLB0/IOTLB1 tag RAM 128x64 (2 parity bits)
       0001: IOTLB0/IOTLB1 data RAM 128x140 (4 parity bits)
       0010: reserved
       0011: reserved
       0100: Context Cache tag RAM 128x32 (1 parity bit)
       0101: Context Cache Data RAM 128x52 (2 parity bits)
       0110: L1/L2 tag RAM 128x40 (2 parity bits)
       0111: L1/L2 Data RAM 128x44 (1 parity bit)
       1000: L3 Tag RAM 128x40 (2 parity bits)
       1001: L3 Data RAM 128x44 (1 parity bit)
       1010-1111: Reserved
       Note: Abnormalities may occur for values 5h, 7h and 9h (refer HSD 2346417).
     */
    UINT32 rsvd_28 : 1;
    /* rsvd_28 - Bits[28:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 errinjst : 1;
    /* errinjst - Bits[29:29], RW1CS, default = 1'b0 
       Error injected status
       0: No error was injected
       1: An error was injected
     */
    UINT32 eirfsel : 1;
    /* eirfsel - Bits[30:30], RWS, default = 1'b0 
       Error Injection Function Select
       0: Select EINJ0 response function.
       1: Select EINJ1 response function.
     */
    UINT32 eien : 1;
    /* eien - Bits[31:31], RWS_L, default = 1'b0 
       Error injection enable
       0: Disable error injection
       1: Enable error injection
     */
  } Bits;
  UINT32 Data;
} VTDPAREINJCTL_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPARERRLOG_IIO_DFX_VTD_REG supported on:                                 */
/*       IVT_EP (0x4003C124)                                                  */
/*       IVT_EX (0x4003C124)                                                  */
/*       HSX (0x4003C124)                                                     */
/*       BDX (0x4003C124)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPARERRLOG_IIO_DFX_VTD_REG 0x12024124
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This debug register contains the log for which buffer/path encountered a parity 
 * error. Each bit corresponds to a given buffer/path. As errors are detected 
 * either from normal operational parity errors or those injected, the 
 * corresponding bit is set. This register accumulates over time the various errors 
 * encountered. A write with all 1\xd5 s will clear this register, a write with a 
 * single bit set to 1 will clear the corresponding bit location in this register. 
 */
typedef union {
  struct {
    UINT32 pelset0 : 3;
    /* pelset0 - Bits[2:0], RW1CS, default = 3'b000 
       Parity Error Log Set0[2]: Parity error detected on pbit[1] of Context Cache Data
       [1]: Parity error detected on pbit[0] of Context Cache Data
       [0]: Parity error detected on pbit[0] of Context cache tag
     */
    UINT32 pelset1 : 4;
    /* pelset1 - Bits[6:3], RW1CS, default = 4'b0000 
       Parity Error Log Set1[6]: Parity error detected on pbit[1] of IOTLB1 tag RAM
       [5]: Parity error detected on pbit[0] of IOTLB1 tag RAM
       [4]: Parity error detected on pbit[1] of IOTLB0 tag RAM
       [3]: Parity error detected on pbit[0] of IOTLB0 tag RAM
     */
    UINT32 pelset2 : 4;
    /* pelset2 - Bits[10:7], RW1CS, default = 4'b0000 
       Parity Error Log Set2[10]: Parity error detected on pbit[3] of IOTLB0 data RAM
       [9]: Parity error detected on pbit[2] of IOTLB0 data RAM
       [8]: Parity error detected on pbit[1] of IOTLB0 data RAM
       [7]: Parity error detected on pbit[0] of IOTLB0 data RAM
     */
    UINT32 pelset2a : 1;
    /* pelset2a - Bits[11:11], RW1CS, default = 1'b0 
       Parity Error Log Set2a[11]: Parity error detected on pbit[1] of L1/L2 tag RAM
     */
    UINT32 pelset3 : 4;
    /* pelset3 - Bits[15:12], RW1CS, default = 4'b0000 
       Parity Error Log Set3[15]: Parity error detected on pbit[3] of IOTLB1 data RAM
       [14]: Parity error detected on pbit[2] of IOTLB1 data RAM
       [13]: Parity error detected on pbit[1] of IOTLB1 data RAM
       [12]: Parity error detected on pbit[0] of IOTLB1 data RAM
     */
    UINT32 pelset3a : 1;
    /* pelset3a - Bits[16:16], RW1CS, default = 1'b0 
       Parity Error Log Set3a[16]: Parity error detected on pbit[1] of L3 tag RAM
     */
    UINT32 pelset4 : 4;
    /* pelset4 - Bits[20:17], RW1CS, default = 4'b0000 
       Parity Error Log Set4[20]: Parity error detected on pbit[0] of L3 data RAM
       [19]: Parity error detected on pbit[0] of L3 tag RAM
       [18]: Parity error detected on pbit[0] of L1/L2 data RAM
       [17]: Parity error detected on pbit[0] of L1/L2 tag RAM
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[31:21], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDPARERRLOG_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDATHR_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C130)                                                  */
/*       IVT_EX (0x4003C130)                                                  */
/*       HSX (0x4003C130)                                                     */
/*       BDX (0x4003C130)                                                     */
/* Register default value:              0x000000CA                            */
#define VTDATHR_IIO_DFX_VTD_REG 0x12024130
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x130
 */
typedef union {
  struct {
    UINT32 str_sel : 4;
    /* str_sel - Bits[3:0], RWS_L, default = 4'b1010 
       1
     */
    UINT32 stp_sel : 4;
    /* stp_sel - Bits[7:4], RWS_L, default = 4'b1100 
       1
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDATHR_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPRIVC1_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x2003C164)                                                  */
/*       IVT_EX (0x2003C164)                                                  */
/*       HSX (0x2003C164)                                                     */
/*       BDX (0x2003C164)                                                     */
/* Register default value:              0x0000                                */
#define VTDPRIVC1_IIO_DFX_VTD_REG 0x12022164
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x164
 */
typedef union {
  struct {
    UINT16 privc1 : 16;
    /* privc1 - Bits[15:0], RWS_L, default = 16'b0000000000000000 
       reserve fro DFT bits.
     */
  } Bits;
  UINT16 Data;
} VTDPRIVC1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPRIVC0_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C168)                                                  */
/*       IVT_EX (0x4003C168)                                                  */
/*       HSX (0x4003C168)                                                     */
/*       BDX (0x4003C168)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPRIVC0_IIO_DFX_VTD_REG 0x12024168
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains VT-d defeature bits. The architectural visible defeatures 
 * are placed here as well. 
 */
typedef union {
  struct {
    UINT32 msirevalen : 1;
    /* msirevalen - Bits[0:0], RWS_L, default = 1'b0 
       MSI Re-evaluation EnableThis will enable the generation of additional MSI 
       message when software reads / clears partial status. This will enable the 
       re-evaluation of status after the software reads / clears the status register 
       [specific for that MSI vector] and will check whether there are any other status 
       bits pending that needs software attention. 
       0:MSI Re-evaluation logic disabled.
       1:MSI Re-evaluation logic enabled.
       Refer to Table 14-65 for usage model details.
     */
    UINT32 msiclapsen : 1;
    /* msiclapsen - Bits[1:1], RWS_L, default = 1'b0 
       MSI Collapsing Enable0: MSI Collapsing Disabled
       If this bit is disabled, then MSI message will be sent for each and every status 
       update done by hardware. 
       Logic: Edge_detect[status0] OR Edge_detect[status1] OR Edge_detect[status2] OR 
       ... 
       1: MSI Collapsing Enable
       If this bit is enabled, then MSI message will be sent only once and will wait 
       until the software clears all the status bits. 
       Logic : Edge_detect [OR (all_status_bits_causing_msi)]
       Refer to Table 14-65 for usage model details.
     */
    UINT32 ltkeep : 1;
    /* ltkeep - Bits[2:2], RWS_L, default = 1'b0 
       LT debug mode to keep features enabled.In LT debug mode the chipset will not 
       disable any LT features or assert LTRESET#, as described already in the TBG 
       C-spec. 
       0: Normal LT operation.
       1: Keep LT features enabled
     */
    UINT32 rsvd_3 : 1;
    /* rsvd_3 - Bits[3:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 tlbcmptoten : 1;
    /* tlbcmptoten - Bits[4:4], RWS_L, default = 1'b0 
       Device IOTLB Completion Time out Test Enable:The bit is used for the pre-silicon 
       validation. 
       0: Normal time out value is used.
       1: 640ns timeout value is used.
     */
    UINT32 tlbcmpto : 2;
    /* tlbcmpto - Bits[6:5], RWS_L, default = 2'b00 
       Device IOTLB completion time out:Following time out value would be used if the 
       test enable bit is cleared (TLBCMPTOTEN=0) 
       00: 64us
       01: 256us
       10: 1s
       11: 16s
     */
    UINT32 tlbnochk : 1;
    /* tlbnochk - Bits[7:7], RWS_L, default = 1'b0 
       IOTLB No checking0: Check the Device IOTLB source ID fro valid completion
       1: Do not check the Device IOTLB Source ID for valid completion
     */
    UINT32 drchkbit : 1;
    /* drchkbit - Bits[8:8], RWS_L, default = 1'b0 
       Debug Register 0 Chicken Bit
     */
    UINT32 rsvd_9 : 3;
    /* rsvd_9 - Bits[11:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 adm : 1;
    /* adm - Bits[12:12], RWS_L, default = 1'b0 
       Address Drain Mode 0: Request to drain the read address first and then by write 
       address. 
       1: Request address draining for both read and write address at the same time.
     */
    UINT32 irp : 1;
    /* irp - Bits[13:13], RWS_L, default = 1'b0 
       Isoch Request Priority enable.0: Azalia request has the highest priority for 
       page walk request. 
       1: Azalia has up to 4 consecutive page walk request priority.
     */
    UINT32 qsten : 1;
    /* qsten - Bits[14:14], RWS_L, default = 1'b0 
       Set Queue Size Test EnableWhen enabled, the length of the invalidation request 
       queue become 40. 
     */
    UINT32 dps : 1;
    /* dps - Bits[15:15], RWS_L, default = 1'b0 
       Disable Priority Selection
     */
    UINT32 fpsr : 1;
    /* fpsr - Bits[16:16], RWS_L, default = 1'b0 
       Force Periodic Switch Retry
     */
    UINT32 bad : 1;
    /* bad - Bits[17:17], RWS_L, default = 1'b0 
       Chicken bit to bypass address draining for Vt-d invalidation command.
     */
    UINT32 invwin : 6;
    /* invwin - Bits[23:18], RWS_L, default = 6'b000000 
       Invalidation WindowControls the minimum window in which the invalidation in 
       progress must remain active. Value is in terms of core clocks. 
     */
    UINT32 rsvd_24 : 1;
    /* rsvd_24 - Bits[24:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dad : 1;
    /* dad - Bits[25:25], RWS_L, default = 1'b0 
       Chicken bit to bypass address draining when TE/IE is turn on(TE/IE goes from 
       0->1). 
       When set, DMA/Interrupt draining is not supported before completing the 
       tranlsation enable(TE/IE, goes from 0 -> 1) command. 
     */
    UINT32 dvt : 1;
    /* dvt - Bits[26:26], RWS_L, default = 1'b0 
       Disable VT-d
     */
    UINT32 ud : 5;
    /* ud - Bits[31:27], RWS_L, default = 5'b00000 
       [31] Chicken bit to disable the GPA_ERR signaling hint for completions from VTd 
       back to the transaction layer 
       0: Fix enabled
       1: Fix disabled
       
       [30] Chicken bit to re-enable the error logging on misc error bit when 
       translation is on 
       0: Fix enabled (logging squashed)
       1: Fix disabled (logging enabled)
       Recommended BIOS setting: 0
       EDS visibility: No
       
       [29] Chicken bit to disable ATS translated request context cache lookup
       0: Fix enabled
       1: Fix disabled
       Recommended BIOS setting: 0
       EDS visibility: No
       
       [28] Chicken bit to disable forcing of TLB to report zero for all counters
       0: Fix enabled
       1: Fix disabled
       Recommended BIOS setting: 0
       EDS visibility: No
       
       [27] reserved
       
     */
  } Bits;
  UINT32 Data;
} VTDPRIVC0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPRIVS0_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C16C)                                                  */
/*       IVT_EX (0x4003C16C)                                                  */
/*       HSX (0x4003C16C)                                                     */
/*       BDX (0x4003C16C)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPRIVS0_IIO_DFX_VTD_REG 0x1202416C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains VT-d status bits.
 */
typedef union {
  struct {
    UINT32 tlbentst0 : 1;
    /* tlbentst0 - Bits[0:0], RW1CS, default = 1'b0 
       TLB entry status bit0: No TLB entries are in commit state
       1: At least one TLB entry are in commit state
     */
    UINT32 tlbentst1 : 1;
    /* tlbentst1 - Bits[1:1], RW1CS, default = 1'b0 
       TLB entry status bit for TLB 10: No TLB entries are in commit state
       1: At least one TLB entry are in commit state
     */
    UINT32 cnxcommtst : 1;
    /* cnxcommtst - Bits[2:2], RW1CS, default = 1'b0 
       Context cache or non-leaf entries status bit0: No Context cache or non-leaf 
       entries are in commit state 
       1: At least one Context cache or non-leaf entries are in commit state
     */
    UINT32 notused : 29;
    /* notused - Bits[31:3], RW1CS, default = 29'b00000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} VTDPRIVS0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPMDFXMAT_0_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C170)                                                  */
/*       IVT_EX (0x4003C170)                                                  */
/*       HSX (0x4003C170)                                                     */
/*       BDX (0x4003C170)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPMDFXMAT_0_IIO_DFX_VTD_REG 0x12024170
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * VTd Perfmon Match for Perfmon Counter 0
 */
typedef union {
  struct {
    UINT32 dfxmat0_0 : 8;
    /* dfxmat0_0 - Bits[7:0], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmat1_0 : 8;
    /* dfxmat1_0 - Bits[15:8], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmat2_0 : 8;
    /* dfxmat2_0 - Bits[23:16], RWS, default = 8'b00000000 
       1
     */
    UINT32 orfloc_0 : 2;
    /* orfloc_0 - Bits[25:24], RWS, default = 2'b00 
       1
     */
    UINT32 div_0 : 2;
    /* div_0 - Bits[27:26], RWS, default = 2'b00 
       1
     */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDPMDFXMAT_0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPMDFXMAT_1_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C174)                                                  */
/*       IVT_EX (0x4003C174)                                                  */
/*       HSX (0x4003C174)                                                     */
/*       BDX (0x4003C174)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPMDFXMAT_1_IIO_DFX_VTD_REG 0x12024174
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * VTd Perfmon Match for Perfmon Counter 0
 */
typedef union {
  struct {
    UINT32 dfxmat0_1 : 8;
    /* dfxmat0_1 - Bits[7:0], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmat1_1 : 8;
    /* dfxmat1_1 - Bits[15:8], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmat2_1 : 8;
    /* dfxmat2_1 - Bits[23:16], RWS, default = 8'b00000000 
       1
     */
    UINT32 orfloc_1 : 2;
    /* orfloc_1 - Bits[25:24], RWS, default = 2'b00 
       1
     */
    UINT32 div_1 : 2;
    /* div_1 - Bits[27:26], RWS, default = 2'b00 
       1
     */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDPMDFXMAT_1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPMDFXMSK_0_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C178)                                                  */
/*       IVT_EX (0x4003C178)                                                  */
/*       HSX (0x4003C178)                                                     */
/*       BDX (0x4003C178)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPMDFXMSK_0_IIO_DFX_VTD_REG 0x12024178
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * VTd perfmon DFx Mask for Perfmon Counter 1
 */
typedef union {
  struct {
    UINT32 dfxmsk0_0 : 8;
    /* dfxmsk0_0 - Bits[7:0], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmsk1_0 : 8;
    /* dfxmsk1_0 - Bits[15:8], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmsk2_0 : 8;
    /* dfxmsk2_0 - Bits[23:16], RWS, default = 8'b00000000 
       1
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDPMDFXMSK_0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDPMDFXMSK_1_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C17C)                                                  */
/*       IVT_EX (0x4003C17C)                                                  */
/*       HSX (0x4003C17C)                                                     */
/*       BDX (0x4003C17C)                                                     */
/* Register default value:              0x00000000                            */
#define VTDPMDFXMSK_1_IIO_DFX_VTD_REG 0x1202417C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * VTd perfmon DFx Mask for Perfmon Counter 1
 */
typedef union {
  struct {
    UINT32 dfxmsk0_1 : 8;
    /* dfxmsk0_1 - Bits[7:0], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmsk1_1 : 8;
    /* dfxmsk1_1 - Bits[15:8], RWS, default = 8'b00000000 
       1
     */
    UINT32 dfxmsk2_1 : 8;
    /* dfxmsk2_1 - Bits[23:16], RWS, default = 8'b00000000 
       1
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VTDPMDFXMSK_1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CB_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG supported on:                         */
/*       HSX (0x4003C200)                                                     */
/*       BDX (0x4003C200)                                                     */
/* Register default value:              0x00000000                            */
#define CB_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG 0x12024200

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tcb4 debug signal sets drives the debug 
 * ring output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_0 : 4;
    /* dbg_ev_swiz_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_1 : 4;
    /* dbg_ev_swiz_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_2 : 4;
    /* dbg_ev_swiz_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_3 : 4;
    /* dbg_ev_swiz_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_4 : 4;
    /* dbg_ev_swiz_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_5 : 4;
    /* dbg_ev_swiz_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_6 : 4;
    /* dbg_ev_swiz_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_7 : 4;
    /* dbg_ev_swiz_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CB_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG supported on:                         */
/*       HSX (0x4003C204)                                                     */
/*       BDX (0x4003C204)                                                     */
/* Register default value:              0x00000000                            */
#define CB_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG 0x12024204

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tcb4 debug signal sets drives the debug 
 * ring output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_8 : 4;
    /* dbg_ev_swiz_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[29:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xor_mode : 1;
    /* xor_mode - Bits[30:30], RWS_L, default = 1'b0 
       Puts the debug muxes into XOR mode instead of MUX mode for scanout coverage.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_mux_en : 1;
    /* dbg_mux_en - Bits[31:31], RWS_L, default = 1'b0 
       Turns on the debug muxes (clocks, etc).
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CB_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG supported on:                          */
/*       HSX (0x4003C208)                                                     */
/*       BDX (0x4003C208)                                                     */
/* Register default value:              0x00000000                            */
#define CB_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG 0x12024208

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tcb4 debug signal sets will be muxed 
 * onto the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 5;
    /* dbg_ev_set_ln_sel_0 - Bits[4:0], RWS_L, default = 5'b00000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 5;
    /* dbg_ev_set_ln_sel_1 - Bits[9:5], RWS_L, default = 5'b00000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 5;
    /* dbg_ev_set_ln_sel_2 - Bits[14:10], RWS_L, default = 5'b00000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 5;
    /* dbg_ev_set_ln_sel_3 - Bits[19:15], RWS_L, default = 5'b00000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_4 : 5;
    /* dbg_ev_set_ln_sel_4 - Bits[24:20], RWS_L, default = 5'b00000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_5 : 5;
    /* dbg_ev_set_ln_sel_5 - Bits[29:25], RWS_L, default = 5'b00000 
       Selects the source for byte lane 5 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CB_DBG_MUX_INT_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG supported on:                          */
/*       HSX (0x4003C20C)                                                     */
/*       BDX (0x4003C20C)                                                     */
/* Register default value:              0x00000000                            */
#define CB_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG 0x1202420C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tcb4 debug signal sets will be muxed 
 * onto the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_6 : 5;
    /* dbg_ev_set_ln_sel_6 - Bits[4:0], RWS_L, default = 5'b00000 
       Selects the source for byte lane 6 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_7 : 5;
    /* dbg_ev_set_ln_sel_7 - Bits[9:5], RWS_L, default = 5'b00000 
       Selects the source for byte lane 7 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_8 : 5;
    /* dbg_ev_set_ln_sel_8 - Bits[14:10], RWS_L, default = 5'b00000 
       Selects the source for byte lane 8 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 17;
    /* rsvd - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CB_DBG_MUX_INT_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* DMAPAREINJCTL_IIO_DFX_VTD_REG supported on:                                */
/*       IVT_EP (0x4003C214)                                                  */
/*       IVT_EX (0x4003C214)                                                  */
/*       HSX (0x4003C214)                                                     */
/*       BDX (0x4003C214)                                                     */
/* Register default value:              0x00000000                            */
#define DMAPAREINJCTL_IIO_DFX_VTD_REG 0x12024214
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains the error injection mask register to determine which 
 * parity bits get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 pf : 16;
    /* pf - Bits[15:0], RWS, default = 16'b0000000000000000 
       Protection Flip bitsThis mask is used to invert the corresponding parity bit 
       assigned to the byte, word, or dword of the data. 
     */
    UINT32 hcnksel : 2;
    /* hcnksel - Bits[17:16], RWS, default = 2'b00 
       Half Chunk Select. This bit field selects which chunk to apply the PF[15:0] bit 
       field. 
       00: Low half cache line/filt, chunk 0 (Bytes 15:00 of data)
       01: Low half cache line/filt, chunk 1 (Bytes 31:16 of data)
       10: High half cache line/filt, chunk 0 (Bytes 47:32 of data)
       11: High half cache line/filt, chunk 1 (Bytes 63:48 of data)
     */
    UINT32 rsvd_18 : 5;
    /* rsvd_18 - Bits[22:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 fpb : 1;
    /* fpb - Bits[23:23], RO, default = 1'b0 
       Flip Poison Bit
     */
    UINT32 bps : 3;
    /* bps - Bits[26:24], RWS, default = 3'b000 
       Buffer-Path select:
       000: Read-Completion descriptor FIFO 32x280 (9 parity bits)
       001: Read-Completion source data FIFO 14x280 (9 parity bits)
       010: Write data FIFO 14x140 (5 parity bits)
       011-100: Reserved
       101: PQ Read-Completion source data FIFO
       110: PQ Write data FIFO
       111: Reserved
     */
    UINT32 rsvd_27 : 2;
    /* rsvd_27 - Bits[28:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 errinjst : 1;
    /* errinjst - Bits[29:29], RW1CS, default = 1'b0 
       Error injected status
       0: No error was injected
       1: An error was injected
     */
    UINT32 eirfsel : 1;
    /* eirfsel - Bits[30:30], RWS, default = 1'b0 
       Error Injection Function Select
       0: Select EINJ0 response function.
       1: Select EINJ1 response function.
       This field is not implemented
       (DMA parity error injection is not triggerable by event)
     */
    UINT32 eien : 1;
    /* eien - Bits[31:31], RWS_L, default = 1'b0 
       Error injection enable
       0: Disable error injection
       1: Enable error injection
     */
  } Bits;
  UINT32 Data;
} DMAPAREINJCTL_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMAERRLOG_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C218)                                                  */
/*       IVT_EX (0x4003C218)                                                  */
/*       HSX (0x4003C218)                                                     */
/*       BDX (0x4003C218)                                                     */
/* Register default value:              0x00000000                            */
#define DMAERRLOG_IIO_DFX_VTD_REG 0x12024218
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * ERRATA Note: This Register is not connected in the current hardware 
 * implementationThis debug register contains the log for which buffer/path 
 * encountered a parity error.Each bit corresponds to a given buffer/path. As 
 * errors are detected either from normal operational parity errors or those 
 * injected, the corresponding bit is set. This register accumulates over time the 
 * various errors encountered. A write with all 1\xd5 s will clear this register, a 
 * write with a single bit set to 1 will clear the corresponding bit location in 
 * this register. 
 *  Note: This register can be set by parity errors other than those injected on 
 * purpose. 
 */
typedef union {
  struct {
    UINT32 pelset0 : 9;
    /* pelset0 - Bits[8:0], RW1CS, default = 9'b000000000 
       Parity Error Log Set0[8]: Parity error detected on pbit[8] of Read-Completion 
       descriptor FIFO 
       [7]: Parity error detected on pbit[7] of Read-Completion descriptor FIFO
       [6]: Parity error detected on pbit[6] of Read-Completion descriptor FIFO
       [5]: Parity error detected on pbit[5] of Read-Completion descriptor FIFO
       [4]: Parity error detected on pbit[4] of Read-Completion descriptor FIFO
       [3]: Parity error detected on pbit[3] of Read-Completion descriptor FIFO
       [2]: Parity error detected on pbit[2] of Read-Completion descriptor FIFO
       [1]: Parity error detected on pbit[1] of Read-Completion descriptor FIFO
       [0]: Parity error detected on pbit[0] of Read-Completion descriptor FIFO
     */
    UINT32 pelset1 : 9;
    /* pelset1 - Bits[17:9], RW1CS, default = 9'b000000000 
       Parity Error Log Set1[17]: Parity error detected on pbit[8] of Read-Completion 
       source data FIFO 
       [16]: Parity error detected on pbit[7] of Read-Completion source data FIFO
       [15]: Parity error detected on pbit[6] of Read-Completion source data FIFO
       [14]: Parity error detected on pbit[5] of Read-Completion source data FIFO
       [13]: Parity error detected on pbit[4] of Read-Completion source data FIFO
       [12]: Parity error detected on pbit[3] of Read-Completion source data FIFO
       [11]: Parity error detected on pbit[2] of Read-Completion source data FIFO
       [10]: Parity error detected on pbit[1] of Read-Completion source data FIFO
       [9]: Parity error detected on pbit[0] of Read-Completion source data FIFO
     */
    UINT32 pelset2 : 5;
    /* pelset2 - Bits[22:18], RW1CS, default = 5'b00000 
       Parity Error Log Set2[22]: Parity error detected on pbit[4] of Write data FIFO0
       [21]: Parity error detected on pbit[3] of Write data FIFO0
       [20]: Parity error detected on pbit[2] of Write data FIFO0
       [19]: Parity error detected on pbit[1] of Write data FIFO0
       [18]: Parity error detected on pbit[0] of Write data FIFO0
     */
    UINT32 pelset3 : 5;
    /* pelset3 - Bits[27:23], RW1CS, default = 5'b00000 
       Parity Error Log Set3[27]: Parity error detected on pbit[4] of Write data FIFO1
       [26]: Parity error detected on pbit[3] of Write data FIFO1
       [25]: Parity error detected on pbit[2] of Write data FIFO1
       [24]: Parity error detected on pbit[1] of Write data FIFO1
       [23]: Parity error detected on pbit[0] of Write data FIFO1
     */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DMAERRLOG_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMACHICKEN0_IIO_DFX_VTD_REG supported on:                                  */
/*       IVT_EP (0x4003C230)                                                  */
/*       IVT_EX (0x4003C230)                                                  */
/*       HSX (0x4003C230)                                                     */
/*       BDX (0x4003C230)                                                     */
/* Register default value:              0x00000000                            */
#define DMACHICKEN0_IIO_DFX_VTD_REG 0x12024230
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x230
 */
typedef union {
  struct {
    UINT32 byte0 : 8;
    /* byte0 - Bits[7:0], RW, default = 8'b00000000  */
    UINT32 byte1 : 8;
    /* byte1 - Bits[15:8], RW, default = 8'b00000000  */
    UINT32 byte2 : 8;
    /* byte2 - Bits[23:16], RW, default = 8'b00000000  */
    UINT32 byte3 : 8;
    /* byte3 - Bits[31:24], RW, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} DMACHICKEN0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMACHICKEN1_IIO_DFX_VTD_REG supported on:                                  */
/*       IVT_EP (0x4003C234)                                                  */
/*       IVT_EX (0x4003C234)                                                  */
/*       HSX (0x4003C234)                                                     */
/*       BDX (0x4003C234)                                                     */
/* Register default value:              0x00000000                            */
#define DMACHICKEN1_IIO_DFX_VTD_REG 0x12024234
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x234
 */
typedef union {
  struct {
    UINT32 byte0 : 8;
    /* byte0 - Bits[7:0], RW, default = 8'b00000000  */
    UINT32 byte1 : 8;
    /* byte1 - Bits[15:8], RW, default = 8'b00000000  */
    UINT32 byte2 : 8;
    /* byte2 - Bits[23:16], RW, default = 8'b00000000  */
    UINT32 byte3 : 8;
    /* byte3 - Bits[31:24], RW, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} DMACHICKEN1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMAINTCOUNT_IIO_DFX_VTD_REG supported on:                                  */
/*       IVT_EP (0x4003C240)                                                  */
/*       IVT_EX (0x4003C240)                                                  */
/*       HSX (0x4003C240)                                                     */
/*       BDX (0x4003C240)                                                     */
/* Register default value:              0x00000000                            */
#define DMAINTCOUNT_IIO_DFX_VTD_REG 0x12024240
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x240
 */
typedef union {
  struct {
    UINT32 dmacnt : 16;
    /* dmacnt - Bits[15:0], RO_V, default = 16'b0000000000000000  */
    UINT32 dma_ch_sel : 3;
    /* dma_ch_sel - Bits[18:16], RW, default = 3'b000  */
    UINT32 rsvd_19 : 1;
    /* rsvd_19 - Bits[19:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pq_intcoalesce_dis : 1;
    /* pq_intcoalesce_dis - Bits[20:20], RW, default = 1'b0  */
    UINT32 rsvd_21 : 11;
    /* rsvd_21 - Bits[31:21], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DMAINTCOUNT_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMAMASTERSM_IIO_DFX_VTD_REG supported on:                                  */
/*       IVT_EP (0x4003C244)                                                  */
/*       IVT_EX (0x4003C244)                                                  */
/*       HSX (0x4003C244)                                                     */
/*       BDX (0x4003C244)                                                     */
/* Register default value:              0x00000000                            */
#define DMAMASTERSM_IIO_DFX_VTD_REG 0x12024244
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x244
 */
typedef union {
  struct {
    UINT32 chstsfsm0 : 3;
    /* chstsfsm0 - Bits[2:0], RO_V, default = 3'b000  */
    UINT32 rsvd_3 : 1;
    /* rsvd_3 - Bits[3:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm1 : 3;
    /* chstsfsm1 - Bits[6:4], RO_V, default = 3'b000  */
    UINT32 rsvd_7 : 1;
    /* rsvd_7 - Bits[7:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm2 : 3;
    /* chstsfsm2 - Bits[10:8], RO_V, default = 3'b000  */
    UINT32 rsvd_11 : 1;
    /* rsvd_11 - Bits[11:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm3 : 3;
    /* chstsfsm3 - Bits[14:12], RO_V, default = 3'b000  */
    UINT32 rsvd_15 : 1;
    /* rsvd_15 - Bits[15:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm4 : 3;
    /* chstsfsm4 - Bits[18:16], RO_V, default = 3'b000  */
    UINT32 rsvd_19 : 1;
    /* rsvd_19 - Bits[19:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm5 : 3;
    /* chstsfsm5 - Bits[22:20], RO_V, default = 3'b000  */
    UINT32 rsvd_23 : 1;
    /* rsvd_23 - Bits[23:23], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm6 : 3;
    /* chstsfsm6 - Bits[26:24], RO_V, default = 3'b000  */
    UINT32 rsvd_27 : 1;
    /* rsvd_27 - Bits[27:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 chstsfsm7 : 3;
    /* chstsfsm7 - Bits[30:28], RO_V, default = 3'b000  */
    UINT32 rsvd_31 : 1;
    /* rsvd_31 - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DMAMASTERSM_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMACHSTSINFO_IIO_DFX_VTD_REG supported on:                                 */
/*       IVT_EP (0x4003C248)                                                  */
/*       IVT_EX (0x4003C248)                                                  */
/*       HSX (0x4003C248)                                                     */
/*       BDX (0x4003C248)                                                     */
/* Register default value:              0x00000000                            */
#define DMACHSTSINFO_IIO_DFX_VTD_REG 0x12024248
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x248
 */
typedef union {
  struct {
    UINT32 chsts_err_lock0 : 1;
    /* chsts_err_lock0 - Bits[0:0], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock1 : 1;
    /* chsts_err_lock1 - Bits[1:1], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock2 : 1;
    /* chsts_err_lock2 - Bits[2:2], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock3 : 1;
    /* chsts_err_lock3 - Bits[3:3], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock4 : 1;
    /* chsts_err_lock4 - Bits[4:4], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock5 : 1;
    /* chsts_err_lock5 - Bits[5:5], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock6 : 1;
    /* chsts_err_lock6 - Bits[6:6], RO_V, default = 1'b0  */
    UINT32 chsts_err_lock7 : 1;
    /* chsts_err_lock7 - Bits[7:7], RO_V, default = 1'b0  */
    UINT32 clr_desc_type_1mb : 8;
    /* clr_desc_type_1mb - Bits[15:8], RW, default = 8'b00000000  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DMACHSTSINFO_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG0_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C24C)                                                  */
/*       IVT_EX (0x4003C24C)                                                  */
/*       HSX (0x4003C24C)                                                     */
/*       BDX (0x4003C24C)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG0_IIO_DFX_VTD_REG 0x1202424C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x24c
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg0 : 32;
    /* cmpdscaddr_1_dbg0 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG1_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C250)                                                  */
/*       IVT_EX (0x4003C250)                                                  */
/*       HSX (0x4003C250)                                                     */
/*       BDX (0x4003C250)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG1_IIO_DFX_VTD_REG 0x12024250
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x250
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg1 : 32;
    /* cmpdscaddr_1_dbg1 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG2_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C254)                                                  */
/*       IVT_EX (0x4003C254)                                                  */
/*       HSX (0x4003C254)                                                     */
/*       BDX (0x4003C254)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG2_IIO_DFX_VTD_REG 0x12024254
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x254
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg2 : 32;
    /* cmpdscaddr_1_dbg2 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG2_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG3_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C258)                                                  */
/*       IVT_EX (0x4003C258)                                                  */
/*       HSX (0x4003C258)                                                     */
/*       BDX (0x4003C258)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG3_IIO_DFX_VTD_REG 0x12024258
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x258
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg3 : 32;
    /* cmpdscaddr_1_dbg3 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG3_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG4_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C25C)                                                  */
/*       IVT_EX (0x4003C25C)                                                  */
/*       HSX (0x4003C25C)                                                     */
/*       BDX (0x4003C25C)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG4_IIO_DFX_VTD_REG 0x1202425C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x25c
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg4 : 32;
    /* cmpdscaddr_1_dbg4 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG4_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG5_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C260)                                                  */
/*       IVT_EX (0x4003C260)                                                  */
/*       HSX (0x4003C260)                                                     */
/*       BDX (0x4003C260)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG5_IIO_DFX_VTD_REG 0x12024260
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x260
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg5 : 32;
    /* cmpdscaddr_1_dbg5 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG5_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG6_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C264)                                                  */
/*       IVT_EX (0x4003C264)                                                  */
/*       HSX (0x4003C264)                                                     */
/*       BDX (0x4003C264)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG6_IIO_DFX_VTD_REG 0x12024264
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x264
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg6 : 32;
    /* cmpdscaddr_1_dbg6 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG6_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CHANSTS_1_DBG7_IIO_DFX_VTD_REG supported on:                               */
/*       IVT_EP (0x4003C268)                                                  */
/*       IVT_EX (0x4003C268)                                                  */
/*       HSX (0x4003C268)                                                     */
/*       BDX (0x4003C268)                                                     */
/* Register default value:              0x00000000                            */
#define CHANSTS_1_DBG7_IIO_DFX_VTD_REG 0x12024268
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x268
 */
typedef union {
  struct {
    UINT32 cmpdscaddr_1_dbg7 : 32;
    /* cmpdscaddr_1_dbg7 - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} CHANSTS_1_DBG7_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* DMAPRIVC0_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C26C)                                                  */
/*       IVT_EX (0x4003C26C)                                                  */
/*       HSX (0x4003C26C)                                                     */
/*       BDX (0x4003C26C)                                                     */
/* Register default value:              0x40020400                            */
#define DMAPRIVC0_IIO_DFX_VTD_REG 0x1202426C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains bit for the design team for DMA defeature bits. The 
 * architectural visible defeatures are placed here as well. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 4;
    /* rsvd_0 - Bits[3:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pdpcdis : 1;
    /* pdpcdis - Bits[4:4], RWS, default = 1'b0 
       Post Dual-align Parity checking. DP ECC error reporting disable 0: Enable post 
       parity checking 
       1: Disable post parity checking
     */
    UINT32 rdmrkdis : 1;
    /* rdmrkdis - Bits[5:5], RWS, default = 1'b0 
       Read marker skipping performance enhancement Disable 0: Enable read marker 
       skipping 
       1: Disable read marker skipping
     */
    UINT32 dspfthdis : 1;
    /* dspfthdis - Bits[6:6], RWS, default = 1'b0 
       Descriptor Prefetch Disable 0: Enable Descriptor prefetch
       1: Disable Descriptor prefetch
     */
    UINT32 npfthdis : 1;
    /* npfthdis - Bits[7:7], RWS, default = 1'b0 
       Notify Prefetch disable 0: Enable Notify prefetch
       1: Disable Notify prefetch
     */
    UINT32 crcrptdis : 1;
    /* crcrptdis - Bits[8:8], RWS, default = 1'b0 
       CRC Error Reporting Disable0: Enable CRC error reporting
       1: Disable CRC error reporting
     */
    UINT32 dribble : 1;
    /* dribble - Bits[9:9], RWS, default = 1'b0 
       Force Dribble Mode. Prefetch sm must wait for rd completion before issuing rfo 
       request 
     */
    UINT32 dma_dca_enable : 1;
    /* dma_dca_enable - Bits[10:10], RWS, default = 1'b1 
       When this field is set to 1, DCA Hint is sent for destination and completion 
       write txns from the DMA-unit. When this field is set to 0, DCA Hint is not sent 
       (Tag = 5'b11111) for any write originating from the DMA-unit. 
     */
    UINT32 disthrottling : 1;
    /* disthrottling - Bits[11:11], RWS, default = 1'b0 
       Disable throttling for dac inbound arbiter
     */
    UINT32 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 concfetchdis : 1;
    /* concfetchdis - Bits[16:16], RWS, default = 1'b0 
       DMA Concurrent Fetch DisableWhen set, disables the concurrent fetch request 
       optimization used to maximize data throughput of the DMA engine. 
       0: Enable concurrent fetch and data transfer (i.e overlapped read/write during 
       fetch phase) for performance (default) 
       1: Disable concurrent fetch operation. i.e. Read and Write fetch requests will 
       be serialized. 
     */
    UINT32 rlxordrmmiow : 1;
    /* rlxordrmmiow - Bits[17:17], RWS, default = 1'b1 
       Relaxed Ordering of DMA MMIO WritesWhen set, enables a weakly ordered model for 
       pushing MMIO writes to the destination I/O device. The weakly ordered model 
       allows for writes to be completed out of order with increased performance since 
       the DMA does not have to wait for the completions (in linear order) from the CE 
       and the overall throughput is higher. 
       0: Disable out-of-order write fetches and enforce serialization of write 
       requests to the destination 
       1: Enable DMA engine to complete out-of-order write fetches to the destination 
       MMIO) for maximizing performance (default). 
       In either mode setting, all writes are completed before a status write or 
       interrupt is generated. 
       In the case of memory to memory transfers, the SG CE acks the fetch completion 
       immediately (when there is no conflict) and since the DMA engine issues fetches 
       inorder, the fetch completions also follow suit and are therefore amenable for 
       pipelining without any reordering penalty for the general case. 
     */
    UINT32 rsvd_18 : 6;
    /* rsvd_18 - Bits[23:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 power_save : 1;
    /* power_save - Bits[24:24], RWS, default = 1'b0 
       Disable driving of debug signals to the debug mux tree for power saving.0: 
       Enable driving of debug signals to the debug ring. (DEFAULT) 
       1: Disable driving of debug signals to the debug ring.
     */
    UINT32 msirevalen : 1;
    /* msirevalen - Bits[25:25], RWS, default = 1'b0 
       MSI Re-evaluation EnableThis will enable the generation of additional MSI 
       message when software reads / clears partial status. This will enable the 
       re-evaluation of status after the software reads / clears the status register 
       [specific for that MSI vector] and will check whether there are any other status 
       bits pending that needs software attention. 
       0:MSI Re-evaluation logic disabled.
       1:MSI Re-evaluation logic enabled.
       Refer to Table 14-65 for usage model details.
     */
    UINT32 msiclapsen : 1;
    /* msiclapsen - Bits[26:26], RWS, default = 1'b0 
       MSI Collapsing Enable0: MSI Collapsing Disabled
       If this bit is disabled, then MSI message will be sent for each and every status 
       update done by hardware. 
       Logic: Edge_detect[status0] OR Edge_detect[status1] OR Edge_detect[status2] OR 
       ... 
       1: MSI Collapsing Enable
       If this bit is enabled, then MSI message will be sent only once and will wait 
       until the software clears all the status bits. 
       Logic : Edge_detect [OR (all_status_bits_causing_msi)]
       Refer to Table 14-65 for usage model details.
     */
    UINT32 rsvd_27 : 3;
    /* rsvd_27 - Bits[29:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 cb_pq_1cl_per_src : 1;
    /* cb_pq_1cl_per_src - Bits[30:30], RWS, default = 1'b1  */
    UINT32 rsvd_31 : 1;
    /* rsvd_31 - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DMAPRIVC0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* CB_IPC_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG supported on:                     */
/*       HSX (0x4003C280)                                                     */
/*       BDX (0x4003C280)                                                     */
/* Register default value:              0x00000000                            */
#define CB_IPC_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_REG 0x12024280

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tipc debug signal sets drives the debug 
 * ring output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_0 : 4;
    /* dbg_ev_swiz_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_1 : 4;
    /* dbg_ev_swiz_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_2 : 4;
    /* dbg_ev_swiz_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_3 : 4;
    /* dbg_ev_swiz_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_4 : 4;
    /* dbg_ev_swiz_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_5 : 4;
    /* dbg_ev_swiz_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_6 : 4;
    /* dbg_ev_swiz_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_swiz_ln_sel_7 : 4;
    /* dbg_ev_swiz_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CB_IPC_DBG_MUX_SWIZ_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_IPC_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG supported on:                     */
/*       HSX (0x4003C284)                                                     */
/*       BDX (0x4003C284)                                                     */
/* Register default value:              0x00000000                            */
#define CB_IPC_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_REG 0x12024284

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tipc debug signal sets drives the debug 
 * ring output. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_swiz_ln_sel_8 : 4;
    /* dbg_ev_swiz_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from the 9 internal debug bus lanes.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[29:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 xor_mode : 1;
    /* xor_mode - Bits[30:30], RWS_L, default = 1'b0 
       Puts the debug muxes into XOR mode instead of MUX mode for scanout coverage.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_mux_en : 1;
    /* dbg_mux_en - Bits[31:31], RWS_L, default = 1'b0 
       Turns on the debug muxes (clocks, etc).
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CB_IPC_DBG_MUX_SWIZ_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_IPC_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG supported on:                      */
/*       HSX (0x4003C288)                                                     */
/*       BDX (0x4003C288)                                                     */
/* Register default value:              0x00000000                            */
#define CB_IPC_DBG_MUX_INT_SEL0_IIO_DFX_VTD_REG 0x12024288

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tipc debug signal sets will be muxed 
 * onto the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_0 : 4;
    /* dbg_ev_set_ln_sel_0 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 0 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_1 : 4;
    /* dbg_ev_set_ln_sel_1 - Bits[7:4], RWS_L, default = 4'b0000 
       Selects the source for byte lane 1 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_2 : 4;
    /* dbg_ev_set_ln_sel_2 - Bits[11:8], RWS_L, default = 4'b0000 
       Selects the source for byte lane 2 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_3 : 4;
    /* dbg_ev_set_ln_sel_3 - Bits[15:12], RWS_L, default = 4'b0000 
       Selects the source for byte lane 3 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_4 : 4;
    /* dbg_ev_set_ln_sel_4 - Bits[19:16], RWS_L, default = 4'b0000 
       Selects the source for byte lane 4 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_5 : 4;
    /* dbg_ev_set_ln_sel_5 - Bits[23:20], RWS_L, default = 4'b0000 
       Selects the source for byte lane 5 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_6 : 4;
    /* dbg_ev_set_ln_sel_6 - Bits[27:24], RWS_L, default = 4'b0000 
       Selects the source for byte lane 6 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbg_ev_set_ln_sel_7 : 4;
    /* dbg_ev_set_ln_sel_7 - Bits[31:28], RWS_L, default = 4'b0000 
       Selects the source for byte lane 7 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CB_IPC_DBG_MUX_INT_SEL0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* CB_IPC_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG supported on:                      */
/*       HSX (0x4003C28C)                                                     */
/*       BDX (0x4003C28C)                                                     */
/* Register default value:              0x00000000                            */
#define CB_IPC_DBG_MUX_INT_SEL1_IIO_DFX_VTD_REG 0x1202428C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register selects which set of iicb/tipc debug signal sets will be muxed 
 * onto the internal debug bus. 
 */
typedef union {
  struct {
    UINT32 dbg_ev_set_ln_sel_8 : 4;
    /* dbg_ev_set_ln_sel_8 - Bits[3:0], RWS_L, default = 4'b0000 
       Selects the source for byte lane 8 from each debug set.
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 28;
    /* rsvd - Bits[31:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CB_IPC_DBG_MUX_INT_SEL1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* IRPP0PAREINJCTL_IIO_DFX_VTD_REG supported on:                              */
/*       IVT_EP (0x4003C320)                                                  */
/*       IVT_EX (0x4003C320)                                                  */
/*       HSX (0x4003C320)                                                     */
/*       BDX (0x4003C320)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0PAREINJCTL_IIO_DFX_VTD_REG 0x12024320
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains the error injection mask register to determine which 
 * parity bits get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 pf : 16;
    /* pf - Bits[15:0], RWS, default = 16'b0000000000000000 
       Protection Flip bits
       This mask is used to invert the corresponding parity bit assigned to the byte, 
       word, or dword of the data. [3:0] are used for hcnksel=00, [7:4] for hcnksel=01. 
     */
    UINT32 hcnksel : 2;
    /* hcnksel - Bits[17:16], RWS, default = 2'b00 
       Half Chunk Select
       This bit field selects which chunk to apply the PF[15:0] bit field.
       00: chunk 0 (Bytes 15:00 of data)
       01: chunk 1 (Bytes 31:16 of data)
       When buffer path select indicates Inbound Pkt RF FIFO then this field set to 00 
       would select data bits 0 to 127 for parity error injection, and this field set 
       to 01 would select data bits 128 to 256 for parity error injection. 
     */
    UINT32 rsvd_18 : 5;
    /* rsvd_18 - Bits[22:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 fpb : 1;
    /* fpb - Bits[23:23], RO, default = 1'b0 
       Flip Poison Bit
     */
    UINT32 bps : 3;
    /* bps - Bits[26:24], RWS, default = 3'b000 
       Buffer-Path select:
       000-010: Reserved
       011: Inbound Pkt RF FIFO
       100-111: Reserved
     */
    UINT32 rsvd_27 : 2;
    /* rsvd_27 - Bits[28:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 errinjst : 1;
    /* errinjst - Bits[29:29], RW1CS, default = 1'b0 
       Error injected status
       0: No error was injected
       1: An error was injected
     */
    UINT32 eirfsel : 1;
    /* eirfsel - Bits[30:30], RWS, default = 1'b0 
       Error Injection Function Select
       0: Select EINJ0 response function.
       1: Select EINJ1 response function.
       (Must enable the IIO global error injection modules to generate the EINJ0 and 
       EINJ1 response functions to feed into the IRP) 
     */
    UINT32 eien : 1;
    /* eien - Bits[31:31], RWS_L, default = 1'b0 
       Error injection enable
       0: Disable error injection
       1: Enable error injection
     */
  } Bits;
  UINT32 Data;
} IRPP0PAREINJCTL_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* IRPP1PAREINJCTL_IIO_DFX_VTD_REG supported on:                              */
/*       IVT_EP (0x4003C324)                                                  */
/*       IVT_EX (0x4003C324)                                                  */
/*       HSX (0x4003C324)                                                     */
/*       BDX (0x4003C324)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1PAREINJCTL_IIO_DFX_VTD_REG 0x12024324
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * This register contains the error injection mask register to determine which 
 * parity bits get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 pf : 16;
    /* pf - Bits[15:0], RWS, default = 16'b0000000000000000 
       Protection Flip bits
       This mask is used to invert the corresponding parity bit assigned to the byte, 
       word, or dword of the data. [3:0] are used for hcnksel=00, [7:4] for hcnksel=01. 
     */
    UINT32 hcnksel : 2;
    /* hcnksel - Bits[17:16], RWS, default = 2'b00 
       Half Chunk Select
       This bit field selects which chunk to apply the PF[15:0] bit field.
       00: chunk 0 (Bytes 15:00 of data)
       01: chunk 1 (Bytes 31:16 of data)
       When buffer path select indicates Inbound Pkt RF FIFO then this field set to 00 
       would select data bits 0 to 127 for parity error injection, and this field set 
       to 01 would select data bits 128 to 256 for parity error injection. 
     */
    UINT32 rsvd_18 : 5;
    /* rsvd_18 - Bits[22:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 fpb : 1;
    /* fpb - Bits[23:23], RO, default = 1'b0 
       Flip Poison Bit
     */
    UINT32 bps : 3;
    /* bps - Bits[26:24], RWS, default = 3'b000 
       Buffer-Path select:
       000-010: Reserved
       011: Inbound Pkt RF FIFO
       100-111: Reserved
     */
    UINT32 rsvd_27 : 2;
    /* rsvd_27 - Bits[28:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 errinjst : 1;
    /* errinjst - Bits[29:29], RW1CS, default = 1'b0 
       Error injected status
       0: No error was injected
       1: An error was injected
     */
    UINT32 eirfsel : 1;
    /* eirfsel - Bits[30:30], RWS, default = 1'b0 
       Error Injection Function Select
       0: Select EINJ0 response function.
       1: Select EINJ1 response function.
       (Must enable the IIO global error injection modules to generate the EINJ0 and 
       EINJ1 response functions to feed into the IRP) 
     */
    UINT32 eien : 1;
    /* eien - Bits[31:31], RWS_L, default = 1'b0 
       Error injection enable
       0: Disable error injection
       1: Enable error injection
     */
  } Bits;
  UINT32 Data;
} IRPP1PAREINJCTL_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* IIRPTHR0_IIO_DFX_VTD_REG supported on:                                     */
/*       IVT_EP (0x4003C330)                                                  */
/*       IVT_EX (0x4003C330)                                                  */
/*       HSX (0x4003C330)                                                     */
/*       BDX (0x4003C330)                                                     */
/* Register default value:              0x000000CA                            */
#define IIRPTHR0_IIO_DFX_VTD_REG 0x12024330
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x330
 */
typedef union {
  struct {
    UINT32 start_sel : 4;
    /* start_sel - Bits[3:0], RWS_L, default = 4'b1010 
       Selects the source which causes the activation of the response in the cluster.
       0000: Global Event 0 (GE[0])
       0001: Global Event 1 (GE[1])
       0010: Global Event 2 (GE[2])
       0011: Global Event 3 (GE[3])
       0100: Artificial Starvation Counter 0 (ASC[0])
       0101: Artificial Starvation Counter 1 (ASC[1])
       0110: Artificial Starvation Counter 2 (ASC[2])
       0111: Artificial Starvation Counter 3 (ASC[3])
       1000: Global Event 4 (GE[4])
       1001: Global Event 5 (GE[5])
       1010: Response never occurs
       1011: Response occurs immediately
       1100-1111: Reserved
     */
    UINT32 stop_sel : 4;
    /* stop_sel - Bits[7:4], RWS_L, default = 4'b1100 
       Selects the source which causes the deactivation of the response in the cluster.
       0000: Global Event 0 (GE[0])
       0001: Global Event 1 (GE[1])
       0010: Global Event 2 (GE[2])
       0011: Global Event 3 (GE[3])
       0100: Artificial Starvation Counter 0 (ASC[0])
       0101: Artificial Starvation Counter 1 (ASC[1])
       0110: Artificial Starvation Counter 2 (ASC[2])
       0111: Artificial Starvation Counter 3 (ASC[3])
       1000: Global Event 4 (GE[4])
       1001: Global Event 5 (GE[5])
       1010: Deactivate one clock after activation. Error injection on one transaction 
       will occur on the interface that is enabled. 
       1011: Response is never deactivated
       1100: Deactivate the response when the activating signal becomes false.
       1101-1111: Reserved
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIRPTHR0_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* IIRPTHR1_IIO_DFX_VTD_REG supported on:                                     */
/*       IVT_EP (0x4003C334)                                                  */
/*       IVT_EX (0x4003C334)                                                  */
/*       HSX (0x4003C334)                                                     */
/*       BDX (0x4003C334)                                                     */
/* Register default value:              0x000000CA                            */
#define IIRPTHR1_IIO_DFX_VTD_REG 0x12024334
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.7.4.CFG.xml.
 * generated by critter 07_4_0x334
 */
typedef union {
  struct {
    UINT32 start_sel : 4;
    /* start_sel - Bits[3:0], RWS_L, default = 4'b1010 
       Selects the source which causes the activation of the response in the cluster.
       0000: Global Event 0 (GE[0])
       0001: Global Event 1 (GE[1])
       0010: Global Event 2 (GE[2])
       0011: Global Event 3 (GE[3])
       0100: Artificial Starvation Counter 0 (ASC[0])
       0101: Artificial Starvation Counter 1 (ASC[1])
       0110: Artificial Starvation Counter 2 (ASC[2])
       0111: Artificial Starvation Counter 3 (ASC[3])
       1000: Global Event 4 (GE[4])
       1001: Global Event 5 (GE[5])
       1010: Response never occurs
       1011: Response occurs immediately
       1100-1111: Reserved
     */
    UINT32 stop_sel : 4;
    /* stop_sel - Bits[7:4], RWS_L, default = 4'b1100 
       Selects the source which causes the deactivation of the response in the cluster.
       0000: Global Event 0 (GE[0])
       0001: Global Event 1 (GE[1])
       0010: Global Event 2 (GE[2])
       0011: Global Event 3 (GE[3])
       0100: Artificial Starvation Counter 0 (ASC[0])
       0101: Artificial Starvation Counter 1 (ASC[1])
       0110: Artificial Starvation Counter 2 (ASC[2])
       0111: Artificial Starvation Counter 3 (ASC[3])
       1000: Global Event 4 (GE[4])
       1001: Global Event 5 (GE[5])
       1010: Deactivate one clock after activation. Error injection on one transaction 
       will occur on the interface that is enabled. 
       1011: Response is never deactivated
       1100: Deactivate the response when the activating signal becomes false.
       1101-1111: Reserved
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIRPTHR1_IIO_DFX_VTD_STRUCT;
#endif /* ASM_INC */


/* VTDRNG_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C104)                                                  */
/*       IVT_EX (0x4003C104)                                                  */
/* Register default value:              0x180000C0                            */
#define VTDRNG_IIO_DFX_VTD_REG 0x12024104



/* VTDDELS_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C108)                                                  */
/*       IVT_EX (0x4003C108)                                                  */
/* Register default value:              0x00000000                            */
#define VTDDELS_IIO_DFX_VTD_REG 0x12024108



/* VTDPDELS0_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C10C)                                                  */
/*       IVT_EX (0x4003C10C)                                                  */
/* Register default value:              0x00000000                            */
#define VTDPDELS0_IIO_DFX_VTD_REG 0x1202410C



/* VTDPDELS1_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C110)                                                  */
/*       IVT_EX (0x4003C110)                                                  */
/* Register default value:              0x00000000                            */
#define VTDPDELS1_IIO_DFX_VTD_REG 0x12024110



/* DMARNG_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C200)                                                  */
/*       IVT_EX (0x4003C200)                                                  */
/* Register default value:              0x18000000                            */
#define DMARNG_IIO_DFX_VTD_REG 0x12024200



/* DMADELS_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C204)                                                  */
/*       IVT_EX (0x4003C204)                                                  */
/* Register default value:              0x00000000                            */
#define DMADELS_IIO_DFX_VTD_REG 0x12024204



/* DMAPDELS0_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C208)                                                  */
/*       IVT_EX (0x4003C208)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS0_IIO_DFX_VTD_REG 0x12024208



/* DMAPDELS1_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C20C)                                                  */
/*       IVT_EX (0x4003C20C)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS1_IIO_DFX_VTD_REG 0x1202420C



/* DMAPDELS2_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C220)                                                  */
/*       IVT_EX (0x4003C220)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS2_IIO_DFX_VTD_REG 0x12024220



/* DMAPDELS3_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C224)                                                  */
/*       IVT_EX (0x4003C224)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS3_IIO_DFX_VTD_REG 0x12024224



/* DMAPDELS4_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C228)                                                  */
/*       IVT_EX (0x4003C228)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS4_IIO_DFX_VTD_REG 0x12024228



/* DMAPDELS5_IIO_DFX_VTD_REG supported on:                                    */
/*       IVT_EP (0x4003C22C)                                                  */
/*       IVT_EX (0x4003C22C)                                                  */
/* Register default value:              0x00000000                            */
#define DMAPDELS5_IIO_DFX_VTD_REG 0x1202422C



/* IOARNG_IIO_DFX_VTD_REG supported on:                                       */
/*       IVT_EP (0x4003C280)                                                  */
/*       IVT_EX (0x4003C280)                                                  */
/* Register default value:              0x180000C0                            */
#define IOARNG_IIO_DFX_VTD_REG 0x12024280



/* IOADELS_IIO_DFX_VTD_REG supported on:                                      */
/*       IVT_EP (0x4003C284)                                                  */
/*       IVT_EX (0x4003C284)                                                  */
/* Register default value:              0x00000000                            */
#define IOADELS_IIO_DFX_VTD_REG 0x12024284



#endif /* IIO_DFX_VTD_h */
